十七
42a4650a78
- 增加STM8 Bootloader工程及出厂固件恢复流程\n- 增加W25Q64外部Flash驱动和OTA分包接收、CRC16校验、断点续传状态管理\n- 增加固件版本查询、升级结果上报与主机确认机制\n- 将业务帧从55 AA帧头调整为发送方Mesh短地址+CMD+LEN+DATA+CRC16\n- 修正JDY-28M外层地址与业务发送方地址的职责划分，支持广播请求定向应答\n- 同步更新硬件引脚、存储分区、OTA流程和主机通信协议文档\n- 已使用SDCC重新编译，应用代码大小为5512字节，链接地址为0x8800
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/**
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* @file stm8s003_registers.h
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* @brief STM8S003F3 常用外设寄存器的最小定义集。
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*
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* 本工程暂不引入完整厂商库，先使用经过数据手册地址核对的最小寄存器集。
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* 后续如果切换到 ST 标准外设库，只应替换本文件和 drivers 层，不改变业务层接口。
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*/
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#ifndef STM8S003_REGISTERS_H
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#define STM8S003_REGISTERS_H
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#include <stdint.h>
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/* GPIO 端口寄存器布局：ODR、IDR、DDR、CR1、CR2。 */
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#define GPIOA_ODR_ADDR 0x5000u
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#define GPIOA_IDR_ADDR 0x5001u
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#define GPIOA_DDR_ADDR 0x5002u
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#define GPIOA_CR1_ADDR 0x5003u
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#define GPIOA_CR2_ADDR 0x5004u
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#define GPIOB_ODR_ADDR 0x5005u
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#define GPIOB_IDR_ADDR 0x5006u
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#define GPIOB_DDR_ADDR 0x5007u
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#define GPIOB_CR1_ADDR 0x5008u
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#define GPIOB_CR2_ADDR 0x5009u
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#define GPIOC_ODR_ADDR 0x500Au
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#define GPIOC_IDR_ADDR 0x500Bu
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#define GPIOC_DDR_ADDR 0x500Cu
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#define GPIOC_CR1_ADDR 0x500Du
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#define GPIOC_CR2_ADDR 0x500Eu
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#define GPIOD_ODR_ADDR 0x500Fu
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#define GPIOD_IDR_ADDR 0x5010u
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#define GPIOD_DDR_ADDR 0x5011u
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#define GPIOD_CR1_ADDR 0x5012u
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#define GPIOD_CR2_ADDR 0x5013u
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#define SPI1_CR1_ADDR 0x5200u
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#define SPI1_CR2_ADDR 0x5201u
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#define SPI1_SR_ADDR 0x5203u
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#define SPI1_DR_ADDR 0x5204u
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/* UART1 寄存器地址。 */
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#define UART1_SR_ADDR 0x5230u
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#define UART1_DR_ADDR 0x5231u
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#define UART1_BRR1_ADDR 0x5232u
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#define UART1_BRR2_ADDR 0x5233u
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#define UART1_CR1_ADDR 0x5234u
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#define UART1_CR2_ADDR 0x5235u
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#define UART1_CR3_ADDR 0x5236u
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#define UART1_CR4_ADDR 0x5237u
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#define UART1_CR5_ADDR 0x5238u
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/* ADC1 寄存器地址。 */
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#define ADC1_CSR_ADDR 0x5400u
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#define ADC1_CR1_ADDR 0x5401u
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#define ADC1_CR2_ADDR 0x5402u
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#define ADC1_CR3_ADDR 0x5403u
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#define ADC1_DRH_ADDR 0x5404u
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#define ADC1_DRL_ADDR 0x5405u
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/* TIM4 低功耗 8 位定时器寄存器地址。 */
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#define TIM4_CR1_ADDR 0x5340u
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#define TIM4_IER_ADDR 0x5343u
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#define TIM4_SR1_ADDR 0x5344u
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#define TIM4_EGR_ADDR 0x5345u
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#define TIM4_CNTR_ADDR 0x5346u
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#define TIM4_PSCR_ADDR 0x5347u
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#define TIM4_ARR_ADDR 0x5348u
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/* 独立看门狗寄存器。 */
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#define IWDG_KR_ADDR 0x50E0u
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#define IWDG_PR_ADDR 0x50E1u
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#define IWDG_RLR_ADDR 0x50E2u
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#define REG8(address) (*((volatile uint8_t *)(address)))
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#define PA1_MASK 0x02u
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#define PA2_MASK 0x04u
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#define PC3_MASK 0x08u
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#define PC4_MASK 0x10u
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/** PC4 在 STM8S003F3P6 上对应 ADC1 的 AIN2 通道。 */
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#define ADC1_CHANNEL_PC4 2u
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#define PD3_MASK 0x08u
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#define PD5_MASK 0x20u
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#define PD6_MASK 0x40u
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#define PC5_MASK 0x20u
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#define PC6_MASK 0x40u
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#define PC7_MASK 0x80u
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#define PD2_MASK 0x04u
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#define PD4_MASK 0x10u
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#define PB5_MASK 0x20u
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#define PB4_MASK 0x10u
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#define SPI1_CR1 REG8(SPI1_CR1_ADDR)
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#define SPI1_CR2 REG8(SPI1_CR2_ADDR)
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#define SPI1_SR REG8(SPI1_SR_ADDR)
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#define SPI1_DR REG8(SPI1_DR_ADDR)
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#define SPI_CR1_SPE 0x40u
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#define SPI_CR1_MSTR 0x04u
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#define SPI_CR1_BR0 0x08u
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#define SPI_CR1_BR1 0x10u
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#define SPI_CR1_BR2 0x20u
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#define SPI_CR2_SSI 0x01u
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#define SPI_CR2_SSM 0x02u
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#define SPI_SR_RXNE 0x01u
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#define SPI_SR_TXE 0x02u
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#endif
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