/** * @file stm8s003_registers.h * @brief STM8S003F3 常用外设寄存器的最小定义集。 * * 本工程暂不引入完整厂商库,先使用经过数据手册地址核对的最小寄存器集。 * 后续如果切换到 ST 标准外设库,只应替换本文件和 drivers 层,不改变业务层接口。 */ #ifndef STM8S003_REGISTERS_H #define STM8S003_REGISTERS_H #include /* GPIO 端口寄存器布局:ODR、IDR、DDR、CR1、CR2。 */ #define GPIOA_ODR_ADDR 0x5000u #define GPIOA_IDR_ADDR 0x5001u #define GPIOA_DDR_ADDR 0x5002u #define GPIOA_CR1_ADDR 0x5003u #define GPIOA_CR2_ADDR 0x5004u #define GPIOB_ODR_ADDR 0x5005u #define GPIOB_IDR_ADDR 0x5006u #define GPIOB_DDR_ADDR 0x5007u #define GPIOB_CR1_ADDR 0x5008u #define GPIOB_CR2_ADDR 0x5009u #define GPIOC_ODR_ADDR 0x500Au #define GPIOC_IDR_ADDR 0x500Bu #define GPIOC_DDR_ADDR 0x500Cu #define GPIOC_CR1_ADDR 0x500Du #define GPIOC_CR2_ADDR 0x500Eu #define GPIOD_ODR_ADDR 0x500Fu #define GPIOD_IDR_ADDR 0x5010u #define GPIOD_DDR_ADDR 0x5011u #define GPIOD_CR1_ADDR 0x5012u #define GPIOD_CR2_ADDR 0x5013u #define SPI1_CR1_ADDR 0x5200u #define SPI1_CR2_ADDR 0x5201u #define SPI1_SR_ADDR 0x5203u #define SPI1_DR_ADDR 0x5204u /* UART1 寄存器地址。 */ #define UART1_SR_ADDR 0x5230u #define UART1_DR_ADDR 0x5231u #define UART1_BRR1_ADDR 0x5232u #define UART1_BRR2_ADDR 0x5233u #define UART1_CR1_ADDR 0x5234u #define UART1_CR2_ADDR 0x5235u #define UART1_CR3_ADDR 0x5236u #define UART1_CR4_ADDR 0x5237u #define UART1_CR5_ADDR 0x5238u /* ADC1 寄存器地址。 */ #define ADC1_CSR_ADDR 0x5400u #define ADC1_CR1_ADDR 0x5401u #define ADC1_CR2_ADDR 0x5402u #define ADC1_CR3_ADDR 0x5403u #define ADC1_DRH_ADDR 0x5404u #define ADC1_DRL_ADDR 0x5405u /* TIM4 低功耗 8 位定时器寄存器地址。 */ #define TIM4_CR1_ADDR 0x5340u #define TIM4_IER_ADDR 0x5343u #define TIM4_SR1_ADDR 0x5344u #define TIM4_EGR_ADDR 0x5345u #define TIM4_CNTR_ADDR 0x5346u #define TIM4_PSCR_ADDR 0x5347u #define TIM4_ARR_ADDR 0x5348u /* 独立看门狗寄存器。 */ #define IWDG_KR_ADDR 0x50E0u #define IWDG_PR_ADDR 0x50E1u #define IWDG_RLR_ADDR 0x50E2u #define REG8(address) (*((volatile uint8_t *)(address))) #define PA1_MASK 0x02u #define PA2_MASK 0x04u #define PC3_MASK 0x08u #define PC4_MASK 0x10u /** PC4 在 STM8S003F3P6 上对应 ADC1 的 AIN2 通道。 */ #define ADC1_CHANNEL_PC4 2u #define PD3_MASK 0x08u #define PD5_MASK 0x20u #define PD6_MASK 0x40u #define PC5_MASK 0x20u #define PC6_MASK 0x40u #define PC7_MASK 0x80u #define PD2_MASK 0x04u #define PD4_MASK 0x10u #define PB5_MASK 0x20u #define PB4_MASK 0x10u #define SPI1_CR1 REG8(SPI1_CR1_ADDR) #define SPI1_CR2 REG8(SPI1_CR2_ADDR) #define SPI1_SR REG8(SPI1_SR_ADDR) #define SPI1_DR REG8(SPI1_DR_ADDR) #define SPI_CR1_SPE 0x40u #define SPI_CR1_MSTR 0x04u #define SPI_CR1_BR0 0x08u #define SPI_CR1_BR1 0x10u #define SPI_CR1_BR2 0x20u #define SPI_CR2_SSI 0x01u #define SPI_CR2_SSM 0x02u #define SPI_SR_RXNE 0x01u #define SPI_SR_TXE 0x02u #endif