feat: 完善Mesh继电器OTA与地址协议

- 增加STM8 Bootloader工程及出厂固件恢复流程\n- 增加W25Q64外部Flash驱动和OTA分包接收、CRC16校验、断点续传状态管理\n- 增加固件版本查询、升级结果上报与主机确认机制\n- 将业务帧从55 AA帧头调整为发送方Mesh短地址+CMD+LEN+DATA+CRC16\n- 修正JDY-28M外层地址与业务发送方地址的职责划分，支持广播请求定向应答\n- 同步更新硬件引脚、存储分区、OTA流程和主机通信协议文档\n- 已使用SDCC重新编译，应用代码大小为5512字节，链接地址为0x8800
2026-11-03 11:29:55 +08:00
parent d275a3523b
commit 42a4650a78
30 changed files with 2318 additions and 108 deletions
@@ -0,0 +1,72 @@
+/**
+ * @file stm8_bootloader_registers.h
+ * @brief Bootloader 使用的 STM8S003F3P6 最小寄存器定义。
+ */
+#ifndef STM8_BOOTLOADER_REGISTERS_H
+#define STM8_BOOTLOADER_REGISTERS_H
+
+#include <stdint.h>
+
+#define REG8(address) (*((volatile uint8_t *)(address)))
+
+/* FLASH 外设寄存器地址，地址来自 STM8S003 数据手册。 */
+#define FLASH_CR1_ADDR  0x505Au
+#define FLASH_CR2_ADDR  0x505Bu
+#define FLASH_NCR2_ADDR 0x505Cu
+#define FLASH_IAPSR_ADDR 0x505Fu
+#define FLASH_PUKR_ADDR 0x5062u
+
+#define FLASH_CR1  REG8(FLASH_CR1_ADDR)
+#define FLASH_CR2  REG8(FLASH_CR2_ADDR)
+#define FLASH_NCR2 REG8(FLASH_NCR2_ADDR)
+#define FLASH_IAPSR REG8(FLASH_IAPSR_ADDR)
+#define FLASH_PUKR REG8(FLASH_PUKR_ADDR)
+
+/* Flash 控制位。 */
+#define FLASH_CR2_PRG  0x01u
+#define FLASH_CR2_WPRG 0x10u
+#define FLASH_IAPSR_HVOFF 0x08u
+
+/* IWDG 寄存器。 */
+#define IWDG_KR_ADDR  0x50E0u
+#define IWDG_PR_ADDR  0x50E1u
+#define IWDG_RLR_ADDR 0x50E2u
+#define IWDG_KR  REG8(IWDG_KR_ADDR)
+#define IWDG_PR  REG8(IWDG_PR_ADDR)
+#define IWDG_RLR REG8(IWDG_RLR_ADDR)
+
+/* SPI1 外设寄存器。 */
+#define SPI1_CR1_ADDR 0x5200u
+#define SPI1_CR2_ADDR 0x5201u
+#define SPI1_ICR_ADDR 0x5202u
+#define SPI1_SR_ADDR  0x5203u
+#define SPI1_DR_ADDR  0x5204u
+#define SPI1_CR1 REG8(SPI1_CR1_ADDR)
+#define SPI1_CR2 REG8(SPI1_CR2_ADDR)
+#define SPI1_SR  REG8(SPI1_SR_ADDR)
+#define SPI1_DR  REG8(SPI1_DR_ADDR)
+
+#define GPIOA_ODR REG8(0x5000u)
+#define GPIOA_IDR REG8(0x5001u)
+#define GPIOA_DDR REG8(0x5002u)
+#define GPIOA_CR1 REG8(0x5003u)
+#define GPIOC_ODR REG8(0x500Au)
+#define GPIOC_DDR REG8(0x500Cu)
+#define GPIOC_CR1 REG8(0x500Du)
+
+#define SPI_CR1_SPE  0x40u
+#define SPI_CR1_MSTR 0x04u
+#define SPI_CR1_BR0  0x08u
+#define SPI_CR1_BR1  0x10u
+#define SPI_CR1_BR2  0x20u
+#define SPI_CR2_SSI  0x01u
+#define SPI_CR2_SSM  0x02u
+#define SPI_SR_RXNE  0x01u
+#define SPI_SR_TXE   0x02u
+#define SPI_SR_BSY   0x80u
+
+#define FLASH_IAPSR_EOP 0x04u
+#define FLASH_CR2_PRG   0x01u
+#define FLASH_CR2_ERASE 0x20u
+
+#endif